//-------------------------------------------------------------------------
//
//  Copyright (c) 1999 Cornell University
//  Computer Systems Laboratory
//  Cornell University, Ithaca, NY 14853
//  All Rights Reserved
//
//  Permission to use, copy, modify, and distribute this software
//  and its documentation for any purpose and without fee is hereby
//  granted, provided that the above copyright notice appear in all
//  copies. Cornell University makes no representations
//  about the suitability of this software for any purpose. It is
//  provided "as is" without express or implied warranty. Export of this
//  software outside of the United States of America may require an
//  export license.
//
//  $Id: mem.v,v 1.1.1.1 2003/01/16 19:49:43 heinrich Exp $
//
//-------------------------------------------------------------------------

`include "mips.h"
   
module mem (I3, Dread, Dwrite, Dsize, State);

input	[31:0]	I3;	// Stage 4 instruction
input   [2:0] 	State;

output		Dread;	// load wants to read memory
reg		Dread;
output		Dwrite;	// store wants to write memory
reg		Dwrite;
output	[1:0]	Dsize;  // data size for a store
reg	[1:0]	Dsize;

//--------------------------------------------------------------------
// As the name implies this is the control logic for the MEM pipe stage.
// The Dread indication is set if the instruction in MEM is some kind of
// load.  On a store it sets the Dwrite flag and also the Dsize variable
// to the size of the store (byte, half-word, word).  The store logic is
// handled external to the chip,in mips.v
//--------------------------------------------------------------------

always @(I3) begin
   if (((I3[`op] == `LW) || (I3[`op] == `LBU) || (I3[`op] == `LB) || (I3[`op] == `LH) || (I3[`op] == `LHU) )) begin
      Dread = 1'b1;
   end   
   else begin
      Dread = 1'b0;
   end

  // if (State == `MEM_STATE) begin
      if (I3[`op] == `SW) begin
	 Dwrite = 1'b1;
	 Dsize = `SIZE_WORD;
      end
      else if (I3[`op] == `SB) begin
	 Dwrite = 1'b1;
	 Dsize = `SIZE_BYTE;
      end
      else if (I3[`op] == `SH) begin
         Dwrite = 1'b1;
         Dsize = `SIZE_HALF;
      end
      else begin
	 Dwrite = 1'b0;
	 Dsize = `SIZE_WORD;
      end
end

//--------------------------------------------------------------------

endmodule			
